The present disclosure relates generally an integrated circuit device and, more particularly, to a gate structure and method of forming a gate of an integrated circuit device.
Providing metal gate structures (e.g., including a metal gate electrode rather than polysilicon) offers one solution to improving IC device performance as technology nodes decrease. One process of forming a metal gate stack is termed “gate last” process in which the final gate stack is fabricated “last” which allows for reduced number of subsequent processes, including high temperature processing, that must be performed after formation of the gate. The “gate last” process including forming a metal gate in a “trench” left by removal of a dummy gate. Additionally, as the dimensions of transistors decrease, the thickness of the gate oxide must be reduced to maintain performance with the decreased gate length. In order to reduce gate leakage, high dielectric constant (high-k) gate insulator layers are used which allow greater physical thicknesses while maintaining the same effective thickness as would be provided by a typical gate oxide used in larger technology nodes.
There are challenges to implementing such features and processes in MOSFET fabrication however. As the gate lengths decrease, these problems are exacerbated. For example, in a “gate last” fabrication process, voiding can occur when depositing a metal film into a trench to from the metal gate electrode. As gate lengths decrease, the trench also decreases in size, and depositing metal into the trench becomes increasingly difficult, and increasingly likely to form a void.
Therefore, what is needed is an improved gate structure and device and method of gate formation.